From 6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5 Mon Sep 17 00:00:00 2001
From: Pasha <pasha@member.fsf.org>
Date: Tue, 20 Feb 2024 18:55:36 +0000
Subject: initial risc-v example

---
 riscv/include/uapi/asm/byteorder.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 riscv/include/uapi/asm/byteorder.h

(limited to 'riscv/include/uapi/asm/byteorder.h')

diff --git a/riscv/include/uapi/asm/byteorder.h b/riscv/include/uapi/asm/byteorder.h
new file mode 100644
index 0000000..f671e16
--- /dev/null
+++ b/riscv/include/uapi/asm/byteorder.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _UAPI_ASM_RISCV_BYTEORDER_H
+#define _UAPI_ASM_RISCV_BYTEORDER_H
+
+#include <linux/byteorder/little_endian.h>
+
+#endif /* _UAPI_ASM_RISCV_BYTEORDER_H */
-- 
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