From ef800d4ffafdbde7d7a172ad73bd984b1695c138 Mon Sep 17 00:00:00 2001
From: Pasha <pasha@member.fsf.org>
Date: Fri, 27 Jan 2023 00:54:07 +0000
Subject: simplex-glpk with modified glpk for fpga

---
 glpk-5.0/examples/plan.mod | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 glpk-5.0/examples/plan.mod

(limited to 'glpk-5.0/examples/plan.mod')

diff --git a/glpk-5.0/examples/plan.mod b/glpk-5.0/examples/plan.mod
new file mode 100644
index 0000000..effe838
--- /dev/null
+++ b/glpk-5.0/examples/plan.mod
@@ -0,0 +1,39 @@
+/* plan.mod */
+
+var bin1, >= 0, <= 200;
+var bin2, >= 0, <= 2500;
+var bin3, >= 400, <= 800;
+var bin4, >= 100, <= 700;
+var bin5, >= 0, <= 1500;
+var alum, >= 0;
+var silicon, >= 0;
+
+minimize
+
+value: .03 * bin1 + .08 * bin2 + .17 * bin3 + .12 * bin4 + .15 * bin5 +
+       .21 * alum + .38 * silicon;
+
+subject to
+
+yield: bin1 + bin2 + bin3 + bin4 + bin5 + alum + silicon = 2000;
+
+fe: .15 * bin1 + .04 * bin2 + .02 * bin3 + .04 * bin4 + .02 * bin5 +
+    .01 * alum + .03 * silicon <= 60;
+
+cu: .03 * bin1 + .05 * bin2 + .08 * bin3 + .02 * bin4 + .06 * bin5 +
+    .01 * alum <= 100;
+
+mn: .02 * bin1 + .04 * bin2 + .01 * bin3 + .02 * bin4 + .02 * bin5
+    <= 40;
+
+mg: .02 * bin1 + .03 * bin2 + .01 * bin5 <= 30;
+
+al: .70 * bin1 + .75 * bin2 + .80 * bin3 + .75 * bin4 + .80 * bin5 +
+    .97 * alum >= 1500;
+
+si: 250 <= .02 * bin1 + .06 * bin2 + .08 * bin3 + .12 * bin4 +
+    .02 * bin5 + .01 * alum + .97 * silicon <= 300;
+
+end;
+
+/* eof */
-- 
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