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| author | Pasha <pasha@member.fsf.org> | 2024-02-20 18:55:36 +0000 |
|---|---|---|
| committer | Pasha <pasha@member.fsf.org> | 2024-02-20 18:55:36 +0000 |
| commit | 6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5 (patch) | |
| tree | 9f5ccbaa6ec19ff5a42d9b3cde01f739e1d7c77d /riscv/include/asm/cache.h | |
| parent | 5e0b8d508ed51004bd836384293be00950ee62c9 (diff) | |
| download | gnumach-riscv-6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5.tar.gz gnumach-riscv-6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5.tar.bz2 | |
Diffstat (limited to 'riscv/include/asm/cache.h')
| -rw-r--r-- | riscv/include/asm/cache.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/riscv/include/asm/cache.h b/riscv/include/asm/cache.h new file mode 100644 index 0000000..2174fe7 --- /dev/null +++ b/riscv/include/asm/cache.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Chen Liqin <liqin.chen@sunplusct.com> + * Copyright (C) 2012 Regents of the University of California + */ + +#ifndef _ASM_RISCV_CACHE_H +#define _ASM_RISCV_CACHE_H + +#define L1_CACHE_SHIFT 6 + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define ARCH_KMALLOC_MINALIGN (8) +#endif + +/* + * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that + * the flat loader aligns it accordingly. + */ +#ifndef CONFIG_MMU +#define ARCH_SLAB_MINALIGN 16 +#endif + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +extern int dma_cache_alignment; +#define dma_get_cache_alignment dma_get_cache_alignment +static inline int dma_get_cache_alignment(void) +{ + return dma_cache_alignment; +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_CACHE_H */ |