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| author | Pasha <pasha@member.fsf.org> | 2024-02-20 18:55:36 +0000 |
|---|---|---|
| committer | Pasha <pasha@member.fsf.org> | 2024-02-20 18:55:36 +0000 |
| commit | 6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5 (patch) | |
| tree | 9f5ccbaa6ec19ff5a42d9b3cde01f739e1d7c77d /riscv/include/asm/perf_event.h | |
| parent | 5e0b8d508ed51004bd836384293be00950ee62c9 (diff) | |
| download | gnumach-riscv-6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5.tar.gz gnumach-riscv-6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5.tar.bz2 | |
Diffstat (limited to 'riscv/include/asm/perf_event.h')
| -rw-r--r-- | riscv/include/asm/perf_event.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/riscv/include/asm/perf_event.h b/riscv/include/asm/perf_event.h new file mode 100644 index 0000000..665bbc9 --- /dev/null +++ b/riscv/include/asm/perf_event.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 SiFive + * Copyright (C) 2018 Andes Technology Corporation + * + */ + +#ifndef _ASM_RISCV_PERF_EVENT_H +#define _ASM_RISCV_PERF_EVENT_H + +#include <linux/perf_event.h> +#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs + +#define perf_arch_fetch_caller_regs(regs, __ip) { \ + (regs)->epc = (__ip); \ + (regs)->s0 = (unsigned long) __builtin_frame_address(0); \ + (regs)->sp = current_stack_pointer; \ + (regs)->status = SR_PP; \ +} +#endif /* _ASM_RISCV_PERF_EVENT_H */ |