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authorPasha <pasha@member.fsf.org>2024-02-20 18:55:36 +0000
committerPasha <pasha@member.fsf.org>2024-02-20 18:55:36 +0000
commit6fca8abef7e6d7be1a9e6d93dd0f2b7fbc5b28e5 (patch)
tree9f5ccbaa6ec19ff5a42d9b3cde01f739e1d7c77d /riscv/include/asm/crash_core.h
parent5e0b8d508ed51004bd836384293be00950ee62c9 (diff)
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initial risc-v exampleHEADmaster
Diffstat (limited to 'riscv/include/asm/crash_core.h')
-rw-r--r--riscv/include/asm/crash_core.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/riscv/include/asm/crash_core.h b/riscv/include/asm/crash_core.h
new file mode 100644
index 0000000..e1874b2
--- /dev/null
+++ b/riscv/include/asm/crash_core.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _RISCV_CRASH_CORE_H
+#define _RISCV_CRASH_CORE_H
+
+#define CRASH_ALIGN PMD_SIZE
+
+#define CRASH_ADDR_LOW_MAX dma32_phys_limit
+#define CRASH_ADDR_HIGH_MAX memblock_end_of_DRAM()
+
+extern phys_addr_t memblock_end_of_DRAM(void);
+#endif